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ISL6721
Data Sheet July 2004 FN9110.2
Flexible Single Ended Current Mode PWM Controller
The ISL6721 is a low power, single-ended pulse width modulating (PWM) current mode controller designed for a wide range of DC-DC conversion applications including boost, flyback, and isolated output configurations. Peak current mode control effectively handles power transients and provides inherent over-current protection. Other features include a low power mode where the supply current drops to less than 200A during over voltage and over current shutdown faults. This advanced BiCMOS design features low operating current, adjustable operating frequency up to 1MHz, adjustable soft-start, and a bi-directional SYNC signal that allows the oscillator to be locked to an external clock for noise sensitive applications.
Features
* 1A MOSFET Gate Driver * 100A Startup Current * Fast Transient Response with Peak Current Mode Control * Adjustable Switching Frequency up to 1MHz * Bi-Directional Synchronization * Low Power Disable Mode * Delayed Restart from OV and OC Shutdown Faults * Adjustable Slope Compensation * Adjustable Soft Start * Adjustable Over Current Shutdown Delay * Adjustable UV and OV Monitors * Leading Edge Blanking * Integrated Thermal Shutdown
Ordering Information
PART NUMBER ISL6721AB ISL6721ABZ (See Note) ISL6721AV ISL6721AVZ (See Note) TEMP. RANGE (oC) -40 to 105 -40 to 105 -40 to 105 -40 to 105 PACKAGE 16 Ld SOIC 16 Ld SOIC (Pb-free) 16 Ld TSSOP 16 Ld TSSOP (Pb-free) PKG. DWG. # M16.15 M16.15 M16.173 M16.173
* 1% Tolerance voltage Reference * Pb-free available
Applications
* Telecom and Datacom Power * Wireless Base Station Power * File Server Power * Industrial Power Systems * Isolated Buck and Flyback Regulators * Boost Regulators
Add "-T" suffix to part number for tape and reel packaging. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
Pinout
ISL6721 (SOIC, TSSOP) TOP VIEW
GATE 1 16 VC 15 PGND 14 VCC 13 VREF 12 LGND 11 SS 10 COMP 9 FB
ISENSE 2 SYNC 3 SLOPE 4 UV 5 OV 6
RTCT 7 ISET 8
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003-2004. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL6721 Functional Block Diagram
VCC START/STOP UV COMPARATOR + BG + LGND THERMAL PROTECTION RESTART DELAY ISET 0.8 ISENSE 5K VREF 53 A + + 100mV + + OVERCURRENT COMPARATOR
Q Q
VREF 5.00 V 1% ENABLE
VREF SOFTSTART CHARGE 70 A CURRENT ON
SS CHARGE VOLTAGE CLAMP
SS OVERCURRENT SHUTDOWN DELAY 25 A + + 15 A
SS CHARGED
4.375V ON
OC DETECT
S R
Q Q
OC LATCH 50 S RETRIGGERABLE ONE SHOT
SLOPE 0.1
SS LOW
+ + -
SS COMP + -
FAULT LATCH SS CLAMP
S R Q Q
270mV SS LOW COMPARATOR
PWM COMPARATOR 2.5V VFB ERROR AMPLIFIER + 1/3 100nS BLANKING START + + VREF 20K 3.0V 1.5V
SET DOMINANT VREF UV COMPARATOR 4.65V + + BG
VREF
+ 12K ON BLANKING COMPARATOR + OSCILLATOR COMPARATOR + 3.0V + -
OV 2.50V UV 1.45V + + -
30K
S
Q Q
VC
RTCT 1mA VREF ON
+
Bi-Directional Synchronization
OSC IN CLK OUT
R
GATE
36K
4V
+ -
NO EXT SYNC
2V
+
EXT SYNC BLANKING SYNC IN VREF SYNC OUT
PGND
100 SYNC 4.5K
2
ISL6721 Typical Application - 48V Input Dual Output Flyback, 3.3V @ 2.5A, 1.8V @ 1.0A
SP1 SP2
CR5 T1 ISO LATIO N XFM R VIN+ P9 R21 +3.3V C21 + C15 + C16
R24
C18 CR4 C19 + C22 + C20
+1.8V
C2 C5
CR2
C17
RET URN CR6 R1 36-75V C6 C1 C3 TP1 Q1 R2 U2 C14 R16 R17 R18 R19
R4 R23
R3
R22 U3 TP2
R15 C13
VIN-
R20
R25 Q2 D1 TP3 SYNC C4 G AT E ISENSE SYNC U4 VC PG ND VCC
ISL6721
SL O PE UV R5 R6 D2 TP5 OV RT CT ISET
VREF LG ND SS CO M P VFB R27 R26
R14
T P4
Q3
C12 R8 R10 C7 R7 R9
C11 C9
VR1
C8 R11 R12 R13
C10
3
ISL6721
Absolute Maximum Ratings
Supply Voltage, VCC, VC . . . . . . . . . . . . . . . . GND - 0.3V to +20.0V GATE . . . . . . . . . . . . . . . . GND - 0.3V to Gate Output Limit Voltage PGND to LGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5.3V Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VREF Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A ESD Classification Human Body Model (Per MIL-STD-883 Method 3015.7) . . .1250V
Thermal Information
Thermal Resistance Junction to Ambient (Typical) JA (oC/W) 16 Lead SOIC (Note 1) . . . . . . . . . . . . . . . . . . . . . . 80 16 Lead TSSOP (Note 1) . . . . . . . . . . . . . . . . . . . . . 105 Maximum Junction Temperature . . . . . . . . . . . . . . . -55oC to 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC, TSSOP - Lead Tips Only)
Operating Conditions
Temperature Range ISL6721Ax . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 105oC Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . . . . 9-18 VDC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. All voltages are with respect to GND.
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application schematic. 9V < VCC = VC < 20V 10%, Rt = 11k, Ct = 330 pF, TA = -40 to 105oC (Note 3), Typical values are at TA = 25oC TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER UNDER VOLTAGE LOCKOUT START Threshold STOP Threshold Hysteresis Start-Up Current, ICC OC/OV Fault Operating Current, ICC Operating Current, ICC Operating Supply Current, IC REFERENCE VOLTAGE Overall Accuracy Long Term Stability Fault Voltage VREF Good Voltage Hysteresis Operational Current Current Limit CURRENT SENSE Input Impedance Offset Voltage Input Voltage Range Blanking Time Gain, ACS
7.95 7.40 0.50 Vcc < START Threshold Includes 1nF GATE loading -
8.25 7.70 0.55 100 200 4.5 8.0
8.55 8.20 1.00 175 300 10.0 12.0
V V V A A mA mA
Line, load, 0 - 105oC Line, load, -40 - 105oC TA = 125oC, 1000 hours (Note 5)
4.95 4.90 4.50 4.65 75 -10 -20
5.00 5.00 5 4.65 4.80 165 -
5.05 5.05 4.75 4.95 250 -
V mV V V mV mA mA
0.08 0 (Note 5) 30 0.77
5 0.10 60 0.79
0.11 1.5 100 0.81
k V V ns V/V
4
ISL6721
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application schematic. 9V < VCC = VC < 20V 10%, Rt = 11k, Ct = 330 pF, TA = -40 to 105oC (Note 3), Typical values are at TA = 25oC (Continued) TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER ERROR AMPLIFIER Open Loop Voltage Gain Gain-Bandwidth Product Reference Voltage Initial Accuracy Reference Voltage COMP to PWM Gain, ACOMP COMP to PWM Offset FB Input Bias Current COMP Sink Current COMP Source Current COMP VOH COMP VOL PSRR SS Clamp, VCOMP OSCILLATOR Frequency Accuracy Frequency Variation with VCC Temperature Stability Minimum Charge and Discharge Time Maximum Duty Cycle Comparator High Threshold - Free Running Comparator High Threshold - with External SYNCH Comparator Low Threshold Discharge Current SYNCHRONIZATION Input High Threshold Input Pulse Width Input Frequency Range Input Impedance VOH VOL SYNCH Advance Output Pulse Width
(Note 5) (Note 5) VFB = COMP, TA = 25oC (Note 5) VFB = COMP COMP = 4V, TA = 25oC COMP = 4V (Note 5) VFB = 0V COMP = 1.5V, VFB = 2.7V COMP = 1.5V, VFB = 2.3V VFB = 2.3V VFB = 2.7V Frequency = 120Hz (Note 5) SS = 2.5V, VFB = 0V, ISET = 2V
60 2.465 2.44 0.31 0.51 -2 2 -0.2 4.25 0.4 60 2.4
90 15 2.515 2.515 0.33 0.75 0.1 6 -0.5 4.4 0.8 80 2.5
2.565 2.590 0.35 0.88 2 5.0 1.2 2.6
dB MHz V V V/V V A mA mA V V dB V
289 T = 105oC (F20V- - F9V)/F9V T = -40oC (F20V- - F9V)/F9V (Note 5) (Note 5) (Note 6) (Note 5) (Note 5) (Note 5) 0 - 105oC -40 - 105oC 68 0.75 0.70
318 2 2 8 TBD 75 3 4 1.5 1.0 1.0
347 3 3 81 1.2 1.2
kHz % % nS % V V V mA
25 (Note 5) 0.65x Free Running RLOAD = 4.5k RLOAD = open SYNCH rising edge to GATE falling edge, CGATE = CSYNCH = 100pF CSYNCH = 100pF 2.5 50
4.5 25 -
2.5 1.0 0.1 55 -
V nS MHz k V V nS nS
5
ISL6721
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application schematic. 9V < VCC = VC < 20V 10%, Rt = 11k, Ct = 330 pF, TA = -40 to 105oC (Note 3), Typical values are at TA = 25oC (Continued) TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER SOFT-START Charging Current Charged Threshold Voltage Initial Over Current Discharge Current Sustained Over Current Threshold Voltage Fault Discharge Current Reset Threshold Voltage SLOPE COMPENSATION Charge Current Slope Compensation Gain Discharge Voltage GATE OUTPUT Gate Output Limit Voltage Gate VOH Gate VOL Peak Output Current Output "Faulted" Leakage Rise Time Fall Time Minimum ON time
SS = 2V
-40 4.26
-55 4.50 40 0.125 1.0 0.27
-70 4.74 55 0.155 0.31
A V A V mA V
Sustained OC Threshold < SS < Charged Threshold Charged Threshold minus SS = 2V
30 0.095 0.25 0.22
SLOPE = 2V, 0 - 105oC -40 - 105oC Fraction of slope voltage added to ISENSE (Note 5) VRTCT = 4.5V
-45 -41 0.095 -
-53 -53 0.100 0.1
-65 -65 0.105 0.2
A V/V V
VC = 20V, CGATE = 1nF, IOUT = 0mA VC - GATE, VC = 10V, IOUT = 150mA GATE - PGND, IOUT = 150mA IOUT = 10mA VC = 20V, CGATE = 1nF (Note 5) VC = 20V, UV = 0V, GATE = 0V GATE = 2V VC = 20V, CGATE = 1nF 1V < GATE < 9V VC = 20V, CGATE = 1nF 1V < GATE < 9V ISET = 0.5V; VFB = 0V; VC = 11V ISENSE to GATE w/10:1 Divider RTCT = 4.75V through 1k (Note 5)
11.0 1.2 -
13.5 1.5 1.2 0.6 1.0 -1 2.6 60 15 -
16.0 2.2 1.5 0.8 -50 100 40 110
V V V A A mA nS nS nS
OVER CURRENT PROTECTION Minimum ISET Voltage Maximum ISET Voltage Restart Delay OV & UV VOLTAGE MONITOR Over Voltage Threshold Under Voltage Fault Threshold Under Voltage Clear Threshold Under Voltage Hysteresis Voltage 2.4 1.38 1.41 20 2.5 1.45 1.53 50 2.6 1.52 1.62 100 V V V mV (Note 5) 1.2 150 295 0.35 445 V V mS
6
ISL6721
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application schematic. 9V < VCC = VC < 20V 10%, Rt = 11k, Ct = 330 pF, TA = -40 to 105oC (Note 3), Typical values are at TA = 25oC (Continued) TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER THERMAL PROTECTION Thermal Shutdown Thermal Shutdown Clear Hysteresis NOTE:
(Note 5) (Note 5) (Note 5)
120 105 -
130 120 10
140 135 -
oC oC oC
3. Specifications at -40oC and 105oC are guaranteed by design, not production tested. 4. This is the VCC current consumed when the device is active but not switching. Does not include gate drive current. 5. Guaranteed by design, not 100% tested in production. 6. This is the maximum duty cycle achievable using the specified values of RT and CT. Larger or smaller maximum duty cycles may be obtained using other values for RT and CT. See Equations 1 - 4.
Typical Performance Curves
NORMALIZED EA REFERENCE Normalized EA Reference
1.002 1.002 NORMALIZED VREF Normalized Vref 1 1 0.998 0.998 0.995 0.995 0.993 0.993 0.991 0.991 -40 40 -10 10 20 20 50 50 80 80 110 110
1.002 1.002 1 1 0.998 0.998 0.995 0.995 0.993 0.993 0.991 0.991 -40 40 -10 10 50 80 50 80 oC Temperature (C) TEMPERATURE 20 20 110 110
Temperature oC TEMPERATURE (C)
FIGURE 1. EA REFERENCE VOLTAGE vs TEMPERATURE
FIGURE 2. VREF REFERENCE VOLTAGE vs TEMPERATURE
NORMALIZED FREQUENCY Normalized Frequency
1.002 1.002 0.996 0.996 0.989 0.989 0.983 0.983 0.976 0.976 0.97 0.97 -40 40 -10 10 20 20 50 50 80 80 110 110
3 1-103 1 .10
FREQUENCY (kHz)
CTCT= =
Frequency (kHz)
100 pF 100pF
100 100
220pF 330pF 470 pF 470pF 680 pF 680pF 1000 pF 1000pF
330 pF
220 pF
Temperature oC TEMPERATURE(C)
FIGURE 3. OSCILLATOR FREQUENCY vs TEMPERATURE
10 10 10 20 10 20
30 30
40 40
50 50
60 60 RT (kohms)
70 70
80 80
90 100 90 100
2200 pF 2000pF
RT (k)
FIGURE 4. CAPACITANCE vs FREQUENCY
7
ISL6721 Pin Descriptions
SLOPE - Means by which the ISENSE ramp slope may be increased for improved noise immunity or improved control loop stability for duty cycles greater than 50%. An internal current source charges an external capacitor to GND during each switching cycle. The resulting ramp is scaled and added to the ISENSE signal. SYNC - A bi-directional synchronization signal used to coordinate the switching frequency of multiple units. Synchronization may be achieved by connecting the SYNC signal of each unit together or by using an external master clock signal. The oscillator timing capacitor, CT, is still required, even if an external clock is used. The first unit to assert this signal assumes control. RTCT - This is the oscillator timing control pin. The operational frequency and maximum duty cycle are set by connecting a resistor, RT, between VREF and this pin and a timing capacitor, CT, from this pin to LGND. The oscillator produces a sawtooth waveform with a programmable frequency range of 100kHz to 1.0MHz. The charge time, TC, the discharge time, TD, the switching frequency, Fsw, and the maximum duty cycle, Dmax, can be calculated from the following equations:
T C 0.655 * R T * C T
OV - Over voltage monitor input pin. This signal is compared to an internal 2.5V reference to detect an over voltage condition. UV - Under voltage monitor input pin. This signal is compared to an internal 1.45V reference to detect an under voltage condition. ISENSE - This is the input to the current sense comparators. The IC has two current sensing comparators, a PWM comparator for peak current mode control, and an over current protection comparator. The over current comparator threshold is adjustable through the ISET pin. Exceeding the over-current threshold will start a delayed shutdown sequence. Once an over current condition is detected, the soft start charge current source is disabled and a discharge current source is enabled. The soft start capacitor begins discharging, and if it discharges to less than 4.375V (Sustained Over Current Threshold), a shutdown condition occurs and the GATE output is forced low. At this point a reduced discharge current takes over until the soft start voltage reaches 0.27V (Reset Threshold). The GATE output remains low until the reset threshold is attained. At this point a soft start cycle begins. If the over current condition ceases, and then an additional 50 S period elapses before the shutdown threshold is reached, no shutdown occurs and the soft start voltage is allowed to recharge. LGND - LGND is a small signal reference ground for all analog functions on this device. PGND - This pin provides a dedicated ground for the output gate driver. The LGND and PGND pins should be connected externally using a short printed circuit board trace close to the IC. This is imperative to prevent large, high frequency switching currents flowing through the ground metallization inside the IC. (Decouple VC to PGND with a low ESR 0.1F or larger capacitor.) GATE - This is the device output. It is a high current power driver capable of driving the gate of a power MOSFET with peak currents of 1.0A. This GATE output is actively held low when VCC is below the UVLO threshold. The output high voltage is clamped to ~ 13.5V. Voltages exceeding this clamp value should not be applied to the GATE pin. The output stage provides very low impedance to overshoot and undershoot. VC - This pin is for separate collector supply to the output gate drive. Separate VC and PGnd helps decouple the IC's analog circuitry from the high power gate drive noise. (Decouple VC to PGND with a low ESR 0.1F or larger capacitor.) VCC - VCC is the power connection for the device. Although quiescent current, ICC, is low, it is dependent on the frequency of operation. To optimize noise immunity, bypass
S
(EQ. 1)
0.001 * R T - 3.6 T D - R * C * LN ------------------------------------------ T T 0.001 * R T - 1.9
S
(EQ. 2)
1 Fsw = -------------------TD + TC
Hz
(EQ. 3)
Dmax = T C * Fsw
(EQ. 4)
Figure 4 may be used as a guideline in selecting the capacitor and resistor values required for a given frequency. COMP - COMP is the output of the error amplifier and the input of the PWM comparator. The control loop frequency compensation network is connected between the COMP and FB pins. The ISL6721 features a built-in full cycle soft start. Soft start is implemented as a clamp on the maximum COMP voltage. FB - Feedback voltage input connected to the inverting input of the error amplifier. The non-inverting input of the error amplifier is internally tied to a reference voltage. Current sense leading edge blanking is disabled when the FB input is less than 2.0V.
8
ISL6721
VCC to LGND with a ceramic capacitor as close to the VCC and LGND pins as possible. The total supply current (IC plus ICC) will be higher, depending on the load applied to GATE. Total current is the sum of the quiescent current and the average gate current. Knowing the operating frequency, Fsw, and the MOSFET gate charge, Qg, the average GATE output current can be calculated from:
Igate = Qg * Fsw A (EQ. 5)
pulse is ignored if it occurs during the first 1/3 of the switching cycle. During normal operation the RTCT voltage charges from 1.5 to 3.0V and back during each cycle. Clock and SYNC signals are generated when the 3.0V threshold is reached. If an external clock signal is detected during the latter 2/3 of the charging cycle, the oscillator switches to external synchronization mode and relies upon the external SYNC signal to terminate the oscillator cycle. The generation of a SYNC signal is inhibited in this mode. If the RTCT voltage exceeds 4.0V (i.e. no external SYNC signal terminates the cycle), the oscillator reverts to the internal clock mode and a SYNC signal is generated.
VREF - The 5.00V reference voltage output. Bypass to LGND with a 0.01F or larger capacitor to filter this output as needed. Using capacitance less than this value may result in unstable operation. SS - Connect the soft start capacitor between this pin and LGND to control the duration of soft start. The value of the capacitor determines both the rate of increase of the duty cycle during start up, and also controls the over current shutdown delay. ISET - A DC voltage between 0.35 and 1.2V applied to this input sets the pulse-by-pulse over current threshold. When over current inception occurs, the SS capacitor begins to discharge and starts the over current delayed shutdown cycle.
Soft-Start Operation
The ISL6721 features soft-start using an external capacitor in conjunction with an internal current source. Soft-start is used to reduce voltage stresses and surge currents during start up. Upon start up, the soft start circuitry clamps the error amplifier output (COMP pin) to a value proportional to the soft start voltage. The error amplifier output rises as the soft start capacitor voltage rises. This has the effect of increasing the output pulse width from zero to the steady state operating duty cycle during the soft start period. When the soft start voltage exceeds the error amplifier voltage, soft start is completed. Soft start forces a controlled output voltage rise. Soft-start occurs during start-up and after recovery from a fault condition or over current shutdown. The soft start voltage is clamped to 4.5V.
Functional Description
Features
The ISL6721 current mode PWMs make an ideal choice for low-cost flyback and forward topology applications requiring enhanced control and supervisory capability. With adjustable over and under voltage thresholds, over current threshold, and hic-cup delay, a highly flexible design with minimal external components is possible. Other features include peak current mode control, adjustable soft-start, slope compensation, adjustable oscillator frequency, and a bidirectional synchronization clock input.
Gate Drive
The ISL6721 is capable of sourcing and sinking 1A peak current. Separate collector supply (VC) and power ground (PGnd) pins help isolate the IC's analog circuitry from the high power gate drive noise. To limit the peak current through the IC, an external resistor may be placed between the totem-pole output of the IC (GATE pin) and the gate of the MOSFET. This small series resistor also damps any oscillations caused by the resonant tank of the parasitic inductances in the traces of the board and the FET's input capacitance.
Oscillator
The ISL6721 have a sawtooth oscillator with a programmable frequency range to 1MHz, which can be programmed with a resistor and capacitor on the RTCT pin. (Please refer to Fig. 4 for the resistance and capacitance required for a given frequency.)
Slope Compensation
For applications where the maximum duty cycle is less than 50%, slope compensation may be used to improve noise immunity, particularly at lighter loads. The amount of slope compensation required for noise immunity is determined empirically, but is generally about 10% of the full scale current feedback signal. For applications where the duty cycle is greater than 50%, slope compensation is required to prevent instability. Slope compensation is a technique in which the current feedback signal is modified by adding additional slope to it. The minimum amount of slope compensation required corresponds to 1/2 the inductor downslope. However, adding excessive slope compensation
Implementing Synchronization
The oscillator can be synchronized to an external clock applied at the SYNC pin or by connecting the SYNC pins of multiple ICs together. If an external master clock signal is used, it must be at least 65% of the free running frequency of the oscillator for proper synchronization. The external master clock signal should have a pulse width greater than 20ns. If no master clock is used, the first device to assert SYNC assumes control of the SYNC signal. An external SYNC
9
ISL6721
results in a control loop that behaves more as a voltage mode controller than as current mode controller.
ISENSE Signal (V) ISENSE SIGNAL (V)
DOWNSLOPE Downslope CURRENT SENSE SIGNAL Current Sense Signal
Otherwise another shutdown cycle occurs. A UV condition also results in a shutdown fault, but the device does not enter the low power mode and no restart delay occurs when the fault clears. A resistor divider between Vin and LGND to each input determines the operational thresholds. The UV threshold has a fixed hysteresis of 75mV nominal.
Over Current Operation
TIME Time
FIGURE 5.
The minimum amount of capacitance to place at the SLOPE pin is:
Cslope = 4.24 x10
-6
The over current threshold level is set by the voltage applied at the ISET pin. Setting the over current level may be accomplished by using a resistor divider network from VREF to LGND. The ISET threshold should be set at a level that corresponds to the desired peak output inductor current plus the additive effects of slope compensation. Over current delayed shutdown is enabled once the soft start cycle is complete. If an over current condition is detected, the soft start charging current source is disabled and the discharging current source is enabled. The soft start capacitor is discharged at a rate of 40A. At the same time a 50S retriggerable one-shot timer is activated. It remains active for 50S after the over current condition stops. The soft start discharge cycle cannot be reset until the one-shot timer becomes inactive. If the soft start capacitor discharges by more then 0.125V to 4.375V, the output is disabled and the soft start capacitor is discharged. The output remains disabled and ICC drops to 200A for approximately 295ms. A new soft start cycle is then initiated. The shutdown and restart behavior of the OC protection is often referred to as hic-cup operation due to its repetitive start-up and shutdown characteristic. If the over current condition ceases at least 50S prior to the soft start voltage reaching 4.375V, the soft start charging and discharging currents revert to normal operation and the soft start voltage is allowed to recover. Hic-cup OC protection may be defeated by setting ISET to a voltage that exceeds the Error Amplifier current control voltage, or about 1.5V.
ton * ------------------Vslope
F
(EQ. 6)
where ton is the On time and Vslope is the amount of voltage to be added as slope compensation to the current feedback signal. In general, the amount of slope compensation added is 2 to 3 times the minimum required. Example: Assume the inductor current signal presented at the ISENSE pin decreases 125mV during the Off period, and: Switching Frequency, Fsw = 250kHz Duty Cycle, D = 60% ton = D/Fsw = 0.6/250E3 = 2.4S toff = (1 - D)/Fsw = 1.6S Determine the downslope: Downslope = 0.125V/1.6S = 78mV/S. Now determine the amount of voltage that must be added to the current sense signal by the end of the On time.
1 Vslope = -- * 0.078 * 2.4 = 94mV 2 (EQ. 7)
Therefore
Cslope ( min ) = 4.24 x10
-6
Leading Edge Blanking
2.4 x10 * ----------------------- 110pF 0.094
-6
(EQ. 8)
An appropriate slope compensation capacitance for this example would be 1/2 to 1/3 the calculated value, or between 68 and 33pF.
The initial 100ns of the current feedback signal input at ISENSE is removed by the leading edge blanking circuitry. The blanking period begins when the GATE output leading edge exceeds 3.0V. Leading edge blanking prevents current spikes from parasitic elements in the power supply from causing false trips of the PWM comparator and the over current comparator.
Over and Under Voltage Monitor
The OV and UV signals are inputs to a window comparator used to monitor the input voltage level to the converter. If the voltage falls outside of the user designated operating range, a shutdown fault occurs. For OV faults, the supply current, ICC, is reduced to 200A for ~ 295ms at which time recovery is attempted. If the fault is cleared, a soft start cycle begins. 10
Fault Conditions
A Fault condition occurs if VREF falls below 4.65V, the OV input exceeds 2.50V, the UV input falls below 1.45V, or the junction temperature of the die exceeds ~130oC. When a Fault is detected the GATE output is disabled and the soft start capacitor is quickly discharged. When the Fault
ISL6721
condition clears and the soft start voltage is below the reset threshold, a soft start cycle begins. Pout: 10W Efficiency: 70% Maximum Duty Cycle, Dmax: 0.45
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the device. A good ground plane must be employed. A unique section of the ground plane must be designated for high di/dt currents associated with the output stage. Power ground (PGND) can be separated from the logic ground (LGND) and connected at a single point. VC should be bypassed directly to PGND with good high frequency capacitors. The return connection for input power and the bulk input capacitor should be connected to the PGND ground plane.
Transformer Design
The design of a flyback transformer is a non-trivial affair. It is an iterative process which requires a great deal of experience to achieve the desired result. It is a process of many compromises, and even experienced designers will produce different designs when presented with identical requirements. The iterative design process is not presented here for clarity. The abbreviated design process follows: * Select a core geometry suitable for the application. Constraints of height, footprint, mounting preference, and operating environment will affect the choice. * Select suitable core material(s). * Select maximum flux density desired for operation. * Select core size. Core size will be dictated by the capability of the core structure to store the required energy, the number of turns that have to be wound, and the wire gauge needed. Often the window area (the space used for the windings) and power loss determine the final core size. For flyback transformers, the ability to store energy is the critical factor in determining the core size. The cross sectional area of the core and the length of the air gap in the magnetic path determine the energy storage capability. * Determine maximum desired flux density. Depending on the frequency of operation, the core material selected, and the operating environment, the allowed flux density must be determined. The decision of what flux density to allow is often difficult to determine initially. Usually the highest flux density that produces an acceptable design is used, but often the winding geometry dictates a larger core than is required based on flux density and energy storage calculations. * Determine the number of primary turns. * Determine the turns ratio. * Select the wire gauge for each winding. * Determine winding order and insulation requirements. * Verify the design.
Reference Design
The Typical Application Schematic features the ISL6721 in a conventional dual output 10W discontinuous mode flyback DC-DC converter. The ISL6721EVAL1 demonstration unit implements this design and is available for evaluation. The input voltage range is from 36 to 75V DC, and the two outputs are 3.3V @ 2.5A and 1.8V @ 1.0A. Cross regulation is achieved using the weighted sum of the two outputs.
Circuit Element Descriptions
The converter design may be broken down into the following functional blocks: Input Storage and Filtering Capacitance: C1, C2, C3 Isolation Transformer: T1 Primary voltage Clamp: CR6, R24, C18 Start Bias Regulator: R1, R2, R6, Q3, VR1 Operating Bias and Regulator: R25, Q2, D1, C5, CR2, D2 Main MOSFET Power Switch: Q1 Current Sense Network: R4, R3, R23, C4 Feedback Network:, R13, R15, R16, R17, R18, R19, R20, R26, R27, C13, C14, U2, U3 Control Circuit:C7, C8, C9, C10, C11, C12, R5, R6, R8, R9, R10, R11, R12, R14, R22 Output Rectification and Filtering: CR4, CR5, C15, C16, C19, C20, C21, C22 Secondary Snubber: R21, C17
Design Criteria
The following design requirements were selected: Switching Frequency, Fsw: 200kHz Vin: 36 - 75V Vout(1): 3.3V @ 2.5A Vout(2): 1.8V @ 1.0A Vout(bias): 12V @ 50mA 11 Input Power: Pout/Efficiency = 14.3W (use 15W) Max On Time: Ton(max) = Dmax/Fsw = 2.25S Average Input Current: Iavg(in) = Pin/Vin(min) = 0.42A
ISL6721
Peak Primary Current:
2 * Iavg ( in ) Ippk = --------------------------------------------- = 1.87 Fsw * Ton ( max ) A (EQ. 9)
lg = 1.56 * 10-3
m
The flux density B is only 0.069T or 690 gauss, a relatively low value. Since
Maximum Primary Inductance:
Vin ( min ) * Ton ( max ) Lp ( max ) = ----------------------------------------------------------- = 43.3 Ippk H (EQ. 10)
o * N p * Aeff L p = ---------------------------------------lg
2
H
(EQ. 13)
Choose desired primary inductance to be 40H. The core structure must be able to deliver a certain amount of energy to the secondary on each switching cycle in order to maintain the specified output power.
Vout + Vd w = Pout * --------------------------------Fsw * Vout joules (EQ. 11)
the number of primary turns, Np, may be calculated. The result is Np = 40 turns. The secondary turns may be calculated as follows:
Ig * Vout + Vd * Tr N s -------------------------------------------------------N p * Ippk * o * Aeff (EQ. 14)
where w is the amount of energy required to be transferred each cycle and Vd is the drop across the output rectifier. The capacity of a gapped ferrite core structure to store energy is dependent on the volume of the airgap and can be expressed as:
2 * o * w Vg = Aeff * lg = ----------------------------2 B m
3
(EQ. 12)
where Aeff is the effective cross sectional area of the core in m2, lg is the length of the airgap in meters, o is the permeability of free space (4 * 10-7), and B is the change in flux density in Tesla. A core structure having less airgap volume than calculated will be incapable of providing the full output power over some portion of its operating range. On the other hand, if the length of the airgap becomes large, magnetic field fringing around the gap occurs. This has the effect of increasing the airgap volume. Some fringing is usually acceptable, but excessive fringing can cause increased losses in the windings around the gap resulting in excessive heating. Once a suitable core and gap combination are found, the iterative design cycle begins. A design is developed and checked for ease of assembly and thermal performance. If the core does not allow adequate space for the windings, then a core with a larger window area is required. If the transformer runs hot, it may be necessary to lower the flux density (more primary turns, lower operating frequency), select a less lossy core material, change the geometry of the windings (winding order), use heavier gauge wire or multifilar windings, and/or change the type of wire used (Litz wire, for example). For simplicity, only the final design is further described. An EPCOS EFD 20/10/7 core using N87 material gapped to an AL value of 25 nH/N2 was chosen. It has more than the required air gap volume to store the energy required, but was needed for the window area it provides. Aeff = 31 * 10-6 m2
where Tr is the time required to reset the core. Since discontinuous MMF mode operation is desired, the core must completely reset during the off time. To maintain discontinuous mode operation, the maximum time allowed to reset the core is Tsw - Ton(max) where Tsw = 1/Fsw. The minimum time is application dependent and at the designers discretion knowing that the secondary winding RMS current and ripple current stress in the output capacitors increases with decreasing reset time. The calculation for maximum Ns for the 3.3 V output using T = Tsw - Ton (max) = 2.75S is 5.52 turns. The determination of the number of secondary turns is also dependent on the number of outputs and the required turns ratios required to generate them. If schottky output rectifiers are used and we assume a forward voltage drop of 0.45V, the required turns ratio for the two output voltages, 3.3V and 1.8V, is 5:3. With a turns ratio of 5:3 for the secondary windings, we will use Ns1 = 5 turns and Ns2 = 3 turns. Checking the reset time using these values for the number of secondary turns yields a duration of Tr = 2.33S or about 47% of the switching period, an acceptable result. The bias winding turns may be calculated similarly, only a diode forward drop of 0.7V is used. The rounded off result is 17 turns for a 12V bias. The next step is to determine the wire gauge. The RMS current in the primary winding may be calculated from:
Ton ( max ) Ip ( rms ) = Ippk * ---------------------------3 * Tsw A (EQ. 15)
The peak and RMS current values in the remaining windings may be calculated from:
2 * Iout * Tsw Ispk = ------------------------------------Tr
A
(EQ. 16)
Tsw Irms = 2 * Iout * -------------3 * Tr
A
(EQ. 17)
12
ISL6721
The RMS current for the primary winding is 0.72A, for the 3.3V output, 4.23A, for the 1.8V output, 1.69A, and for the bias winding, 85mA. To minimize the transformer leakage inductance, the primary was split into two sections connected in parallel and positioned such that the other windings were sandwiched between them. The output windings were configured so that the 1.8V winding is a tap off of the 3.3V winding. Tapping the 1.8V output requires that the shared portion of the secondary conduct the combined current of both outputs. The secondary wire gauge must be selected accordingly. The determination of current carrying capacity of wire is a compromise between performance, size, and cost. It is affected by many design constraints such as operating frequency (harmonic content of the waveform) and the winding proximity/geometry. It generally ranges between 250 and 1000 circular mils per ampere. A circular mil is defined as the area of a circle 0.001" (1 mil) in diameter. As the frequency of operation increases, the AC resistance of the wire increases due to skin and proximity effects. Using heavier gauge wire may not alleviate the problem. Instead multiple strands of wire in parallel must be used. In some cases Litz wire is required. The winding configuration selected is: Primary #1: 40T, 2 #30 bifilar Secondary: 5T, 0.003" (3 mil) copper foil tapped at 3T Bias: 17T #32 Primary #2: 40T, 2 #30 bifilar The internal spacing and insulation system was designed for 1500 VDC dielectric withstand rating between the primary and secondary windings. where Rdson is the ON resistance of the MOSFET and Iprms is the RMS primary current. Determining the conduction losses is complicated by the variation of Rdson with temperature. As junction temperature increases, so does Rdson, which increases losses and raises the junction temperature more, and so on. It is possible for the device to enter a thermal runaway situation without proper heatsinking. As a general rule of thumb, doubling the 25oC Rdson specification yields a reasonable value for estimating the conduction losses at 125oC junction temperature. The switching losses have two components, capacitive switching losses and voltage/current overlap losses. The capacitive losses occur during turn on of the device and may be calculated as follows:
2 1 Pswcap = -- * Cfet * Vin * Fsw 2
W
(EQ. 19)
where Cfet is the equivalent output capacitance of the MOSFET. Device output capacitance is specified on datasheets as Coss and is non-linear with applied voltage. To find the equivalent discrete capacitance, Cfet, a charge model is used. Using a known current source, the time required to charge the MOSFET drain to the desired operating voltage is determined and the equivalent capacitance may be calculated.
Ichg * t Cfet = ------------------V F (EQ. 20)
The other component of the switching loss is due to the overlap of voltage and current during the switching transition. A switching transition occurs when the MOSFET is in the process of either turning on or off. Since the load is inductive, there is no overlap of voltage and current during the turn on transition, so only the turn off transition is of significance. The power dissipation may be estimated as:
1 Psw -- * Ippk * Vin * Tol * Fsw x (EQ. 21)
Power MOSFET Selection
Selection of the main switching MOSFET requires consideration of the voltage and current stresses that will be encountered in the application, the power dissipated by the device, its size, and its cost. The input voltage range of the converter is 36 - 75V DC. This suggests a MOSFET with a voltage rating of 150V is required due to the flyback voltage likely to be seen on the primary of the isolation transformer. The losses associated with MOSFET operation may be divided into three categories: conduction, switching, and gate drive. The conduction losses are due to the MOSFET's ON resistance.
Pcond = Rdson * Iprms
2
where Tol is the duration of the overlap period and x ranges from about 3 - 6 in typical applications and depends on where the waveforms intersect. This estimate may predict higher dissipation than is realized because a portion of the turn off drain current is attributable to the charging of the device output capacitance (Coss) and is not dissipative during this portion of the switching cycle.
Ip pk
W
(EQ. 18)
V D -S Tol
FIGURE 6.
13
ISL6721
The final component of MOSFET loss is caused by the charging of the gate capacitance through the device gate resistance. Depending on the relative value of any external resistance in the gate drive circuit, a portion of this power will be dissipated externally.
Pgate = Qg * Vg * Fsw W (EQ. 22)
The change in voltage due to the change in charge of the output capacitor, Q, determines how much capacitance is required on the output.
( Ispk - Iout ) * Tr ( 10.73 - 2.5 ) * 2.33 x10 C --------------------------------------------- = ------------------------------------------------------------------ = 960F 2 * V 2 * 0.010 (EQ. 24)
-6
Once the losses are known, the device package must be selected and the heatsinking method designed. Since the design requires a small surface mount part, a SOIC-8 package was selected. A Fairchild FDS2570 MOSFET was selected based on these criteria. The overall losses are estimated at 400mW.
ESL adds to the ripple and noise voltage in proportion to the rate of change of current into the capacitor (V = L * di/dt).
V * dt L -------------- = 0.030 * 200 x10 - = 0.56nH --------------------------------------------di 10.73
-9
(EQ. 25)
Output Filter Design
In a flyback design, the primary concern for the design of the output filter is the capacitor ripple current stress and the ripple and noise specification of the output. The current flowing in and out of the output capacitors is the difference between the winding current and the output current. The peak secondary current, Ispk, is 10.73A for the 3.3V output and 4.29A for the 1.8V output. The current flowing into the output filter capacitor is the difference between the winding current and the output current. Looking at the 3.3V output, the peak winding current is Ispk = 10.73A. The capacitor must store this amount minus the output current of 2.5A, or 8.23A. The RMS ripple current in the 3.3V output capacitor is about 3.5 Arms. The RMS ripple current in the 1.8V output capacitor is about 1.4 Arms Voltage deviation on the output during the switching cycle (ripple and noise) is caused by the change in charge of the output capacitance, the equivalent series resistance (ESR), and equivalent series inductance (ESL). Each of these components must be assigned a portion of the total ripple and noise specification. How much to allow for each contributor is dependent on the capacitor technology used. For purposes of this discussion we will assume the following: 3.3V output: 100mV total output ripple and noise ESR: 60mV Capacitor Q: 10mV ESL: 30mV 1.8V output: 50mV total output ripple and noise ESR: 30mV Capacitor Q: 5mV ESL: 15mV For the 3.3V output:
V 0.060 ESR ----------------------------- = ---------------------------- = 7.3m Ispk - Iout 10.73 - 2.5 (EQ. 23)
Capacitors having high capacitance usually do not have sufficiently low ESL. High frequency capacitors such as surface mount ceramic or film are connected in parallel with the high capacitance capacitors to address the effects of ESL. A combination of high frequency and high ripple capability capacitors is used to achieve the desired overall performance. The analysis of the 1.8V output is similar to that of the 3.3V output and is omitted for brevity. Two OSCON 4SEP560M (560F) electrolytic capacitors and a 22F X5R ceramic 1210 capacitor were selected for both the 3.3 and 1.8V outputs. The 4SEP560M electrolytic capacitors are each rated at 4520mA ripple current and 13m of ESR. The ripple current rating of just one of these capacitors is adequate, but two are needed to meet the minimum ESR and capacitance values. The bias output is of such low power and current that it places negligible stress on its filter capacitor. A single 0.1F ceramic capacitor was selected.
Control Loop Design
The major components of the feedback control loop are a programmable shunt regulator, an opto-coupler, and the inverting amplifier of the ISL6721. The opto-coupler is used to transfer the error signal across the isolation barrier. The opto-coupler offers a convenient means to cross the isolation barrier, but it adds complexity to the feedback control loop. It adds a pole at about 10kHz and a significant amount of gain variation due the current transfer ratio (CTR). The CTR of the opto-coupler varies with initial tolerance, temperature, forward current, and age.
14
ISL6721
A block diagram of the feedback control loop follows in Figure 7.
PRIMARY SIDE AMPLIFIER
REF Z3
+ PWM -
POWER STAGE
VOUT
determining ISET, the internal gain and offset of the ISENSE signal in the control IC must be taken into account. The maximum peak primary current was determined earlier to be 1.87A, so a choice of 2.25A peak primary current for current limit is reasonable. A current gain, AEXT, of 0.5 V/A was selected to achieve this.
ISET = 2.25 * 0.8 * 0.5 + 0.100 = 1.00 V (EQ. 26)
Z4 ERROR AMPLIFIER
ISOLATION
Z2
The control to output transfer function may be represented as [2]
+ REF Z1
s 1 + -----z R o * L s * F sw vo ----- = K * ----------------------------------- * ---------------svc 2 1 + -----p
(EQ. 27)
FIGURE 7.
if we ignore the current feedback sampled-data effects.
I spk ( max ) K = ------------------------V c ( max ) R o = LoadResis tan ce L s = SecondaryInduc tan ce 2 p = ------------------Ro * Co 1 z = ------------------Rc * Co or or 1 f p = ---------------------------- * Ro * Co 1 f z = ------------------------------------2 * * Rc * Co
The loop compensation is placed around the Error Amplifier (EA) on the secondary side of the converter. The primary side amplifier located in the control IC is used as a unity gain inverting amplifier and provides no loop compensation. A Type 2 error amplifier configuration was selected as a precaution in case operation in continuous mode should occur at some operating point.
Vout
C o = OutputCapaci tan ce
Verror + REF
R c = OutputCapaci tan ceE SR V c ( max ) = ControlVoltageRange
FIGURE 8. TYPE 2 ERROR AMPLIFIER
Development of a small signal model for current mode control is rather complex. The method of reference [1] was selected for its ability to accurately predict loop behavior. To further simplify the analysis, the converter will be modeled as a single output supply with all of the output capacitance reflected to the 3.3V output. Once the "single" output system is compensated, adjustments to the compensation will be required based on actual loop measurements. The first parameter to determine is the peak current feedback loop gain. Since this application is low power, a resistor in series with the source of the power switching MOSFET is used for the current feedback signal. For higher power applications, a resistor would dissipate too much power and current transformer would be used instead. There is limited flexibility to adjust the current loop behavior due to the need to provide over current protection. Current limit and the current loop gain are determined by the current sense resistor and the ISET threshold. ISET was set at 1.0V, near its maximum, to minimize noise effects. When 15
The value of K may be determined by assuming all of the output power is delivered by the 3.3V output at the threshold of current limit. The maximum power allowed was determined earlier as 15 watts, so
P out -6 15 2 * ----------- * Tsw 2 * ------- * 5 x10 V out 3.3 I spk ( max ) = -------------------------------------- = ----------------------------------------- = 19.5 -6 Tr 2.33 x10 1 v c ( max ) = V ISENSE * A EXT * A CS * -------------------- = 2.93 A
COMP
A
V
where AEXT is the external gain of the current feedback network, ACS is the IC internal gain, and ACOMP is the gain between the error amplifier and the PWM comparator. The Type 2 compensation configuration has two poles and one zero. The first pole is at the origin, and provides the integration characteristic which results in excellent DC regulation. Referring to the Typical Application Schematic,
ISL6721
the remaining pole and zero for the compensator are located at:
C 13 + C 14 1 f pc = ------------------------------------------------------------ ------------------------------------------2 * * R 15 * C 14 * C 13 2 * * R 15 * C 14 (EQ. 28)
A Bode plot of the closed loop system at low line, max load appears below.
50 50 40 40 30 30 20 20 10 10 0 0 -10 10 -20 20 -30 30 -40 40 -50 50 0.01 0.01
1 f zc = ------------------------------------------2 * * R 15 * C 13
(EQ. 29)
The ratio of R15 to the parallel combination of R17 and R18 determine the mid band gain of the error amplifier.
R 15 * ( R 17 + R 18 ) A midband = ----------------------------------------------R 17 * R 18
GAIN (dB)
Gain (dB)
0.1 0.1
1 10 1 10 FREQUENCY (kHz) Frequency (kHz)
100 100
(EQ. 30)
FIGURE 9A. GAIN
Phase MARGIN (degrees) PHASE Margin (degrees)
From (EQ. 27), it can be seen that the control to output transfer function frequency dependence is a function of the output load resistance, the value of output capacitance, and the output capacitance ESR. These variations must be considered when compensating the control loop. The worst case small signal operating point for the converter is at minimum Vin, maximum load, maximum Cout, and minimum ESR. The higher the desired bandwidth of the converter, the more difficult it is to create a solution that is stable over the entire operating range. A good rule of thumb is to limit the bandwidth to about Fsw/4. For this example, the bandwidth will be further limited due to the low GBWP of the LM431based Error Amplifier and the opto-coupler. A bandwidth of approximately 5kHz was selected. For the EA compensation, the first pole is placed at the origin by default (C14 is an integrating capacitor). The first zero is placed below the crossover frequency, fco, usually around 1/3 fco. The second pole is placed at the lower of the ESR zero or at one half of the switching frequency. The midband gain is then adjusted to obtain the desired crossover frequency. If the phase margin is not adequate, the crossover frequency may have to be reduced. Using this technique to determine the compensation, the following values for the EA components were selected. R17 = R18 = R15 = 1k R20 = open C13 = 100nF C14 = 100pF
200 200 150 150 100 100 50 50 0 0 -50 50 -100 100 0.01 0.01 0.1 1 10 0.1 1 10 FREQUENCY (kHz) Frequency (kHz) 100 100
FIGURE 9B. PHASE MARGIN
16
ISL6721
Regulation Performance
TABLE 1. OUTPUT LOAD REGULATION, VIN = 48V IOUT (A), 3.3V 0 0.39 0.88 1.38 1.87 2.39 2.89 3.37 0 0.39 0.88 1.38 1.87 2.39 2.89 0 0.39 0.88 1.38 1.87 2.39 0 0.39 0.88 1.38 1.87 0 0.39 0.88 1.38 0 0.39 0.88 0 .39 IOUT (A), 1.8V VOUT (V), 3.3V VOUT (V), 1.8V 0.030 0.030 0.030 0.030 0.030 0.030 0030 0.030 0.52 0.52 0.52 0.52 0.52 0.52 0.52 1.05 1.05 1.05 1.05 1.05 1.05 1.55 1.55 1.55 1.55 1.55 2.07 2.07 2.07 2.07 2.62 2.62 2.62 3.14 3.14 3.351 3.281 3.251 3.223 3.204 3.185 3.168 3.153 3.471 3.283 3.254 3.233 3.218 3.203 3.191 3.619 3.290 3.254 3.235 3.220 3.207 3.699 3.306 3.260 3.239 3.224 3.762 3.329 3.270 3.245 3.819 3.355 3.282 3.869 3.383 1.825 1.956 1.988 2.014 2.029 2.057 2.084 2.103 1.497 1.800 1.836 1.848 1.855 1.859 1.862 1.347 1.730 1.785 1.805 1.814 1.820 1.265 1.682 1.750 1.776 1.789 1.201 1.645 1.722 1.752 1.142 1.612 1.697 1.091 1.581 NOTE: Trace 1: SYNC Output Trace 2: RTCT Sawtooth Trace 3: GATE Output FIGURE 10. TYPICAL WAVEFORMS
4.375V OC fault threshold at which point the IC enters the fault shutdown mode. Trace 2 shows the behavior of the timing capacitor voltage during a shutdown fault. Most of the functions of the IC are de-powered during a fault, and the oscillator is among those functions. During a fault, the IC is turned off until the restart delay has timed out. After the delay, power is restored and the IC resumes normal operation. Trace 3 is the GATE output during the soft start cycle and OC fault.
Waveforms
Typical waveforms can be found in Figures 10 through 12. Figure 10 shows the steady state operation of the sawtooth oscillator waveform at RTCT (Trace 2), the SYNC output pulse (Trace 1), and the GATE output to the converter FET (Trace 3). Figure 11 shows the converter behavior while operating in an over current fault condition. Trace 1 is the soft start voltage, which increases from zero to 4.5V, at which point the OC fault function is enabled. The OC condition is detected and the soft start capacitor is discharged to the 17
NOTE: Trace 1: SS Trace 2: RTCT Sawtooth Trace 3: GATE Output FIGURE 11. SOFT START W/OVER CURRENT FAULT
Figure 12 shows the switching FET waveforms during steady state operation. Trace 1 is drain - source voltage and Trace 2 is gate - source voltage.
ISL6721
TABLE 2. (Continued) REFERENCE DESIGNATOR R7, R9, R11, R26, R27 R12 R13, R15, R17, R18, R19, R25 R14 R16 R21 R22 R24 NOTE: Trace 1: VD-S Trace 3: VG-S FIGURE 12. GATE AND DRAIN-SOURCE WAVEFORMS R3, R23 R4 R5 R6 R8, R20 TABLE 2. REFERENCE DESIGNATOR C1, C2, C3 C5, C13 C15, C16, C19, C20 C17 C18 C21, C22 C4, C14 C6 C7 C8 C9, C10, C11, C12 CR2, CR6 CR4, CR5 D1 D2 Q1 Q2 Q3 R1, R2 R10 1.00K 20.0K 330pF 0.22F VALUE 1.0F 0.1F 560F 470pF .01F 22F 100pF 1500pF DESCRIPTION U3 Capacitor, 1812, X7R, 100V, 20% U4 Capacitor, 0603, X7R, 25V, 10% VR1 Capacitor, Radial, SANYO 4SEP560M Zener, 15V, Zetex BZX84C15 PWM, Intersil ISL6721IB Shunt Reference, National LM431BIM3 T1 U2 VALUE 10.0K 38.3K 1.00K 10 165 10.0 5.11 3.92K 100 1.00 221K 75.0K DESCRIPTION Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 1206, 1% Resistor, 0603, 1% Resistor, 2512, 1% Resistor, 0603, 1% Resistor, 2512, 1% Resistor, 0603, 1% Resistor, 0603, 1% OMIT Transformer, MIDCOM 31555 Opto-coupler, NEC PS2801-1
Component List
References
Capacitor, 0603, COG, 50V, 5% Capacitor, 0805, X7R, 50V, 10% Capacitor, 1210, X5R, 10V, 20% Capacitor, 0603, COG, 50V, 5% Capacitor, Disc, Murata DE1E3KX152MA5BA01 Zero Ohm Jumper, 0603 Capacitor, 0603, COG, 50V, 5% Capacitor, 0603, X7R, 16V, 10% Diode, Fairchild ES1C Diode, IR 12CWQ03FN Zener, 18V, Zetex BZX84C18 Diode, Schottky, BAT54C FET, Fairchild FDS2570 Transistor, Zetex FMMT491A Transistor, ON MJD31C Resistor, 1206, 1% Resistor, 0603, 1%
[1] Ridley, R., "A New Continuous-Time Model for Current Mode Control", IEEE Transactions on Power Electronics, Vol. 6, No. 2, April 1991. [2] Dixon, Lloyd H., "Closing the Feedback Loop", Unitrode Power Supply Design Seminar, SEM-700, 1990.
18
ISL6721 Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 L 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 GAUGE PLANE 0.25(0.010) M BM
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.033 0.0075 0.0035 0.193 0.169 MAX 0.043 0.006 0.037 0.012 0.008 0.201 0.177 MILLIMETERS MIN 0.05 0.85 0.19 0.09 4.90 4.30 MAX 1.10 0.15 0.95 0.30 0.20 5.10 4.50 NOTES 9 3 4 6 7 8o Rev. 1 2/02
A1 0.10(0.004) A2 c
E1 e E L N
e
b 0.10(0.004) M C AM BS
0.026 BSC 0.246 0.020 16 0o 8o 0.256 0.028
0.65 BSC 6.25 0.50 16 0o 6.50 0.70
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AB, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
19
ISL6721 Small Outline Plastic Packages (SOIC)
N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45o 0.25(0.010) M BM
M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL A A1 B MIN 0.053 0.004 0.014 0.007 0.386 0.150 MAX 0.069 0.010 0.019 0.010 0.394 0.157 MILLIMETERS MIN 1.35 0.10 0.35 0.19 9.80 3.80 MAX 1.75 0.25 0.49 0.25 10.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 1 02/02
L
C D E e H h
C
0.050 BSC 0.228 0.010 0.016 16 0o 8o 0.244 0.020 0.050
1.27 BSC 5.80 0.25 0.40 16 0o 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS

A1 0.10(0.004)
L N
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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